The present invention relates to a semiconductor charge transfer device using a semiconductor charge transfer element such as CCD or BBD and, more particularly, improvements of the interface to transfer signal charge packets from the semiconductor charge transfer element to a sense amplifier.
In construction of a dynamic memory using CCD, for example, the signal charge packet must be detected when it remains at distinguishable level and then refreshed, in order to compensate for the reduction of the signal level resulting from the fact that, in the CCD mode, charge transfer is necessarily accompanied by leaving a little amount of charges in the packet well. To operate the CCD as a dynamic memory for dynamically storing signals (data), a closed loop must be formed in which the output signal from the CCD is detected and refreshed and fed back to the input stage of the CCD. In construction of such memories, a detecting device with good performances such as sensitivity, stability, response and the like is one of very important constitutional components.
By convention, signal charge packets are transferred to the detection node of the CCD, i.e. the floating diffusion region preset; the potential change at the detection node due to incoming signal charge packets is detected by a detecting circuit of inverter type or flip-flop type. The detecting system of the type in which the detection node is connected to the gate of the drive transistor of the inverter, is defective in the sensitivity and the response rate. A differential type detecting circuit is preferable in order to avoid erroneous operation of the system due to the variation of manufacturing or operational conditions of the components used.
One form of the differential type detecting circuits is a flip-flop type detecting circuit frequently used in the MOS type dynamic RAM or the like. Unlike the case of RAM needing the refreshing operation by the positive feedback to the detection node, in the CCD the back current of charge packets from the detection node must be prevented in order to avoid adverse interference. Therefore, it is said that it is difficult to directly use the detecting circuit system for the RAM for the CCD. One of the flip-flop type detecting circuits which has been proposed and practically used in order to avoid such the problem is of the type in which the detection node is coupled with the load transistor of the flip-flop. The exemplar thereof is shown in FIG. 1. As shown, the flip-flop is comprised of n-channel MOS transistors Q1 to Q4. The output of the CCD 2 is inputted to one load transistor Q3 and the reference signal from a reference charge generator 3 is inputted to the other load transistor Q4. See IEEE JOURNAL OF SOLID-STATE CIRCUITS, FEB., 1976, page 37.
This system, however, suffers some problems: the output signal, particularly at high level is susceptible to the signal charge level; the power consumption is large since it is of the called ratio type. The DC power consumption due to the ratio type is problematic in the low power operational mode at the idling of the CCD by low frequency drive.
In the FIG. 1 system, a clock signal .PHI..sub.1 is made high in level when a clock .PHI..sub.2 is at low level so that the n-channel MOS transistors Q5 and Q6 are turned on to precharge both the nodes A and B. Then, after the clock signal .PHI..sub.1 is at low level, charges fed from the CCD 2 and the reference charge generating device 3 are fed to the nodes A and B, respectively, to provide a difference of potential between the A and B nodes. At this time, nodes C and D become low in level. As the clock signal .PHI..sub.2 raises to the high level, the potentials at the nodes C and D raise to the high level. In this case, the difference potential between the nodes A and B brings about a difference between the potential increasing rates at the nodes C and D. Therefore, the potential at one of these nodes increases to reach the threshold level of each drive transistor Q1 and Q2, before the one at the other reaches it. In this case, the former forces the latter to be at the low level. As a result, one of the nodes C and D is stabilized at high level while the other node is stabilized at the low level, permitting the signal charge detection of the CCD 2.
In a normal operation, the potentials at the nodes C and D raise slightly at the initial stage. Therefore, when the potentials at these nodes are used as the input signal of the succeeding stage, it possibly brings about an erroneous operation. For this reason, the flip-flop 1 must be run considerably rapidly than the succeeding stage. Alternately, the response rate of the succeeding stage must be considerably slow. The high level at the output of the flip-flop 1 is V.sub.A -V.sub.TH at the node C and V.sub.B -V.sub.TH at the node D when V.sub.A &gt;V.sub.B. In the relation, V.sub.A and V.sub.B are the potentials at the nodes A and B and V.sub.TH represents the gate threshold potential of each MOS transistor Q3 and Q4. V.sub.B is the output of the reference charge generating device 3 and thus constant. V.sub.A depends on the output of the CCD 2 so that the high level V.sub.A -V.sub.TH at the node C changes depending on the amount of the signal charges fed from the CCD 2. Further, the operation rate of the flip-flop depends largely on the difference of potential between the nodes A and B.
The FIG. 1 system is basically of the ratio type. To operate the FIG. 1 system in the ratioless mode by additionally using transistors and clock signals, the charges at the nodes C and D are discharged to stabilize the potentials thereat and then the A and B nodes are made low level and the load tansistors Q3 and Q4 must be turned off. When the nodes A and B fall to V.sub.SS at the potential level for turning off the transistors Q3 and Q4, charges flow backward to the CCD 2. Accordingly, the feature of the FIG. 1 system which is devised to prevent the back current of charges, is meaningless.